Planarization methods, such as, for example, chemical-mechanical polishing, are commonly used in semiconductor fabrication processes. An exemplary process which utilizes planarization methods is trench isolation region fabrication. Trench isolation regions generally comprise a trench or cavity formed within the substrate and filled with an insulative material, such as, for example, silicon dioxide. Trench isolation regions are commonly divided into three categories: shallow trenches (trenches less than about one micron deep); moderate depth trenches (trenches of about one to about three microns deep); and deep trenches (trenches greater than about three microns deep).
A prior art method for forming trench isolation regions is described with reference to FIGS. 1-9. Referring to FIG. 1, a semiconductor wafer fragment 10 is shown at a preliminary stage of the prior art processing sequence. Wafer fragment 10 comprises a semiconductive material 12 upon which is formed a layer of oxide 14, a layer of nitride 16, and a patterned layer of photoresist 18. Semiconductive material 12 commonly comprises monocrystalline silicon which is lightly doped with a conductivity-enhancing dopant. To aid in interpretation of the claims that follow, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.
Oxide layer 14 typically comprises silicon dioxide, and nitride layer 16 typically comprises silicon nitride. Oxide layer 14 can consist essentially of silicon dioxide, and nitride layer 16 can consist essentially of silicon nitride. Nitride layer 16 is generally from about 400 Angstroms thick to about 1500 Angstroms thick.
Referring to FIG. 2, patterned photoresist layer 18 is used as a mask for an etching process. The etch is typically conducted utilizing dry plasma conditions and CH2F2/CF4 chemistry. Such etching effectively etches both silicon nitride layer 16 and pad oxide layer 14 to form openings 20 extending therethrough. The etching stops upon reaching silicon substrate 12. The etching into nitride layer 16 defines upper corners 22 of the portions of the nitride layer remaining over substrate 12.
Referring to FIG. 3, a second etch is conducted to extend openings 20 into silicon substrate 12. The second etch is commonly referred to as a “trench initiation etch.” The trench initiation etch is typically a timed dry plasma etch utilizing CF4/HBr, and typically extends openings 20 to less than or equal to about 500 Angstroms into substrate 12.
Referring to FIG. 4, a third etch is conducted to extend openings 20 further into substrate 12 and thereby form trenches within substrate 12. The third etch typically utilizes an etchant consisting entirely of HBr, and is typically a timed etch. The timing of the etch is adjusted to form trenches within substrate 12 to a desired depth. For instance, if openings 20 are to be shallow trenches, the third etch will be timed to extend openings 20 to a depth of less than or equal to about one micron.
Referring to FIG. 5, photoresist layer 18 (FIG. 4) is removed and a first oxide fill layer 24 is thermally grown within openings 20.
Referring to FIG. 6, a high density plasma oxide 28 is formed to fill openings 20 (FIG. 5) and overlie nitride layer 16. High density plasma oxide 28 merges with oxide layer 24 (FIG. 5) to form oxide plugs 30 within openings 20 (FIG. 5).
Referring to FIG. 7, wafer fragment 10 is subjected to planarization (such as, for example, chemical-mechanical polishing) to planarize an upper surface of oxide plugs 30. The planarization utilizes a chemistry selective for the oxide material of layer 24 (FIG. 5) relative to the material of nitride layer 16. Accordingly, nitride layer 16 functions as an etch-stop, and the planarization stops at an upper surface of nitride layer 16.
Referring to FIG. 8, nitride layer 16 is removed to expose pad oxide layer 14 between oxide plugs 30. Subsequent processing (not shown) can then be conducted to form a polysilicon layer over and between oxide plugs 30, and to form transistor devices from the polysilicon layer. The regions between oxide plugs 30 are active regions for such transistor devices, and oxide plugs 30 are trench isolation regions separating the transistor devices.
A difficulty of the above-discussed prior art isolation-region-forming method is described with reference to FIG. 9, which illustrates a top view of wafer fragment 10 at the processing step shown in FIG. 7. Specifically, FIG. 9 illustrates a top view of wafer fragment 10 after a planarization process.
Planarization processes typically comprise polishing processes wherein an abrasive material is rubbed against a layer that is to be planarized. For example, chemical-mechanical polishing of oxide material 28 (FIG. 6) involves rubbing a grit-containing slurry against oxide material 28. The slurry is intended to form an interface between a polishing pad and wafer fragment 10 such that the pad does not physically contact portions of wafer fragment 10. However, if there exists particles in the slurry, shear thickening of the slurry, or contact of pad to substrate, then portions of the etch stopping layer, along with portions of the substrate, can be chipped away. This can result in defects which render the device to be made inoperable.
FIG. 9 illustrates that the planarization process has chipped corners 22 of nitride layers 16 to remove portions of the nitride layers and form divots 40. Some of the nitride chipped from corners 22 has become lodged between the polishing pad and wafer fragment 10 during the planarization process. The lodged nitride scratches nitride layers 16 and oxide material 30 as it is spun by the polishing pad to form spiral scratches 42 extending across nitride layer 16 and oxide material 30. Divots 40 and scratches 42 damage oxide regions 30 and can adversely impact further processing and utilization of wafer fragment 10. Accordingly, it would be desirable to develop methods which alleviate chipping of etch-stop layers during planarization processes.